A State Minimization Algorithm for Communicating State Machines With Arbitrary Data Space

A fundamental issue in the automated analysis of communicating systems is the efficient generation of the reachable state space. Since it is not possible to generate all the reachable states of a system with an infinite number of states, we need a way to combine sets of states. In this paper, we describe communicating state machines with data variables, which we use to specify concurrent systems. We then present an algorithm that constructs the minimal reachability graph of a labeled transition system with infinite data values. Our algorithm clusters a set of states that are bisimilar into an equivalent class. We include an example to illustrate our algorithm and identify a set of sufficient conditions that guarantees the termination of the algorithm

An Efficient State Space Generation for the Analysis of Real-Time Systems

State explosion is a well-known problem that impedes analysis and testing based on state-space exploration. This problem is particularly serious in real-time systems because unbounded time values cause the state space to be infinite even for simple systems. In this paper, we present an algorithm that produces a compact representation of the reachable state space of a real-time system. The algorithm yields a small state space, but still retains enough information for analysis. To avoid the state explosion which can be caused by simply adding time values to states, our algorithm uses history equivalence and transition bisimulation to collapse states into equivalent classes. Through history equivalence, states are merged into an equivalence class with the same untimed executions up to the states. Using transition bisimulation, the states that have the same future behaviors are further collapsed. The resultant state space is finite and can be used to analyze real-time properties. To show the effectiveness of our algorithm, we have implemented the algorithm and have analyzed several example applications

Formal Verification of Security Model Using SPR Tool

In this paper, formal verification methodologies and the SPR (Safety Problem Resolver) model checking tool are used for verifying a security model's safety. The SPR tool makes it possible to analyze security issues on security systems based on the access control model. To illustrate this approach, a case study of the Simple Access Control Model (SACM) is used and specific safety problems of the security model are analyzed using the SPR tool

Process Algebraic Approach to the Schedulability Analysis and Workload Abstraction of Hierarchical Real-Time Systems

Real-time embedded systems have increased in complexity. As microprocessors become more powerful, the software complexity of real-time embedded systems has increased steadily. The requirements for increased functionality and adaptability make the development of real-time embedded software complex and error-prone. Component-based design has been widely accepted as a compositional approach to facilitate the design of complex systems. It provides a means for decomposing a complex system into simpler subsystems and composing the subsystems in a hierarchical manner. A system composed of real-time subsystems with hierarchy is called a hierarchical real-time system This paper describes a process algebraic approach to schedulability analysis of hierarchical real-time systems. To facilitate modeling and analyzing hierarchical real-time systems, we conservatively extend an existing process algebraic theory based on ACSR-VP (Algebra of Communicating Shared Resources with Value-Passing) for the schedulability of real-time systems. We explain a method to model a resource model in ACSR-VP which may be partitioned for a subsystem. We also introduce schedulability relation to define the schedulability of hierarchical real-time systems and show that satisfaction checking of the relation is reducible to deadlock checking in ACSR-VP and can be done automatically by the tool support of ERSA (Verification, Execution and Rewrite System for ACSR). With the schedulability relation, we present algorithms for abstracting real-time system workloads

Formal Modeling and Verification of Motor Drive Software for Networked Motion Control Systems

Abstract: This paper presents a model-based approach to the design and verification of motor drive software for networked motion control systems. We develop a formal model for an Ethernetbased motion system, where, using timed automata, we describe the concurrent and synchronized behaviors of the components, i.e., motion controller, motor drives, and communication links. The drive, in particular, is modeled in enough detail to accurately reflect the software implementation used in a real drive. We use the design of multitasked drive software with fixed-priority preemptive scheduling. With UPPAAL model checking, we verify the precision and accuracy of the rendered motion in terms of the requirements on the actuation delay at each drive and the actuation deviation between different drives, respectively. The analysis results demonstrate the benefits of our model-based approach in the safety verification and design space exploration of motor drive software. We show that it is possible to verify deadlock freeness and real-time schedulability in an early design phase. And, for varying number of drives and size of messages, we can successfully determine the combination of task periods that leads to the best precision and accuracy

Regulation of proliferation and invasion by the IGF signalling pathway in Epstein-Barr virus-positive gastric cancer

Several carcinomas including gastric cancer have been reported to contain Epstein-Barr virus (EBV) infection. EBV-associated gastric cancer (EBVaGC) is classified as one of four molecular subtypes of gastric cancer by The Cancer Genome Atlas (TCGA) group with increased immune-related signatures. Identification of EBV-dependent pathways with significant biological roles is needed for EBVaGC. To compare the biological changes between AGS gastric epithelial cells and EBV-infected AGS (AGS-EBV) cells, proliferation assay, CCK-8 assay, invasion assay, cell cycle analysis, RT-PCR, Western blot and ELISA were performed. BI836845, a humanized insulin-like growth factor (IGF) ligand-neutralizing antibody, was used for IGF-related signalling pathway inhibition. AGS-EBV cells showed slower proliferating rate and higher sensitivity to BI836845 compared to AGS cells. Moreover, invasiveness of AGS-EBV was increased than that of AGS, and BI836845 treatment significantly decreased the invasiveness of AGS-EBV. Although no apoptosis was detected, entry into the S phase of the cell cycle was delayed in BI836845-treated AGS-EBV cells. In conclusion, AGS-EBV cells seem to modulate their proliferation and invasion through the IGF signalling pathway. Inhibition of the IGF signalling pathway therefore could be a potential therapeutic strategy for EBVaGC

Real-time system analysis based on state-space exploration

The traditional approach for analyzing correctness of systems is to identify a set of reachable states and then to analyze this set for verification. This approach is called state-space exploration. State-space exploration is widely used because it can be easily automated. However, verification methods based on state-space exploration suffer from state explosion, so they are impractical for verifying systems with large state spaces. We propose a method for state-space reduction to cope with the state explosion, especially that caused by large time space. The state-space reduction is crucial because in general, the complexities of existing algorithms for automatic analysis, e.g. model-checking, depend on the size of the state space. Our state reduction approach uses Communicating Timed State Machine (CTSM), a state machine-based formal model, to describe real-time systems. In CTSM, a system consists of concurrent processes communicating with each other through channels. Each process has special variables called clocks to express various timing constraints such as delays and deadlines. For a CTSM process, there can be an infinite number of states due to time and data values. Our goal is to generate the smallest representation of the reachable states of a CTSM process. For timed-state space reduction, we first collapse states into an equivalence class using the notions of history equivalence and transition bisimulation. In this approach, equivalent states have identical observable events although transitions into the states may happen at different times. The algorithm then augments the resultant state space with timing relations that describe time distances between transition executions. Using this reduced state space, we analyze properties such as reachability, and other properties described in linear-time temporal logic. We have developed an automatic analysis tool based on approaches we have presented in this thesis, called Timed Reachability Analysis Tool (TREAT). It accepts input in CTSM and produces a timed reachability graph, from which users analyze the correctness of the given system. Using TREAT, we show the efficiency of our algorithm and make a comparison with other existing tools by case studies of well-known real-time system examples: the railroad crossing control system, the Fischer\u27s mutual exclusion protocol, the active structure control system, and the Philips audio control protocol

Real-time system analysis based on state-space exploration

The traditional approach for analyzing correctness of systems is to identify a set of reachable states and then to analyze this set for verification. This approach is called state-space exploration. State-space exploration is widely used because it can be easily automated. However, verification methods based on state-space exploration suffer from state explosion, so they are impractical for verifying systems with large state spaces. We propose a method for state-space reduction to cope with the state explosion, especially that caused by large time space. The state-space reduction is crucial because in general, the complexities of existing algorithms for automatic analysis, e.g. model-checking, depend on the size of the state space. Our state reduction approach uses Communicating Timed State Machine (CTSM), a state machine-based formal model, to describe real-time systems. In CTSM, a system consists of concurrent processes communicating with each other through channels. Each process has special variables called clocks to express various timing constraints such as delays and deadlines. For a CTSM process, there can be an infinite number of states due to time and data values. Our goal is to generate the smallest representation of the reachable states of a CTSM process. For timed-state space reduction, we first collapse states into an equivalence class using the notions of history equivalence and transition bisimulation. In this approach, equivalent states have identical observable events although transitions into the states may happen at different times. The algorithm then augments the resultant state space with timing relations that describe time distances between transition executions. Using this reduced state space, we analyze properties such as reachability, and other properties described in linear-time temporal logic. We have developed an automatic analysis tool based on approaches we have presented in this thesis, called Timed Reachability Analysis Tool (TREAT). It accepts input in CTSM and produces a timed reachability graph, from which users analyze the correctness of the given system. Using TREAT, we show the efficiency of our algorithm and make a comparison with other existing tools by case studies of well-known real-time system examples: the railroad crossing control system, the Fischer\u27s mutual exclusion protocol, the active structure control system, and the Philips audio control protocol